The location X must be seen with values A and B in that order. In other words, if location X received two different values A and B, in this order, from any two processors, the processors can never read location X as B and then read it as A. Writes to the same location must be sequenced.Therefore, in order to satisfy Transaction Serialization, and hence achieve Cache Coherence, the following condition along with the previous two mentioned in this section must be met: The processors P3 and P4 now have an incoherent view of the memory. P4 on the other hand may see changes made by P1 and P2 in the order in which they are made and hence return 20 on a read to S. However, P3 may see the change made by P1 after seeing the change made by P2 and hence return 10 on a read to S. If we ensure only write propagation, then P3 and P4 will certainly see the changes made to S by P1 and P2. Processor P1 changes the value of S (in its cached copy) to 10 following which processor P2 changes the value of S in its own cached copy to 20. To illustrate this better, consider the following example:Ī multi-processor system consists of four processors - P1, P2, P3 and P4, all containing cached copies of a shared variable S whose initial value is 0. However, they are not sufficient as they do not satisfy the Transaction Serialization condition. The above conditions satisfy the Write Propagation criteria required for cache coherence. If processor P1 reads the old value of X, even after the write by P2, we can say that the memory is incoherent.
Propagating the writes to the shared memory location ensures that all the caches have a coherent view of the memory. This condition defines the concept of coherent view of memory.
In a multiprocessor system, consider that more than one processor has cached a copy of the memory location X. One type of data occurring simultaneously in different cache memory is called cache coherence, or in some systems, global memory. Definition Ĭoherence defines the behavior of reads and writes to a single address location. However, in practice it is generally performed at the granularity of cache blocks. Theoretically, coherence can be performed at the load/store granularity. Transaction Serialization Reads/Writes to a single memory location must be seen by all processors in the same order. The following are the requirements for cache coherence: Write Propagation Changes to the data in any cache must be propagated to other copies (of that cache line) in the peer caches. Cache coherence is the discipline which ensures that the changes in the values of shared operands (data) are propagated throughout the system in a timely fashion. When one of the copies of data is changed, the other copies must reflect that change. In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. Cache coherence is intended to manage such conflicts by maintaining a coherent view of the data values in multiple caches.Ĭoherent caches: The value in all the caches' copies is the same. Suppose the client on the bottom updates/changes that memory block, the client on the top could be left with an invalid cache of memory without any notification of the change. In the illustration on the right, consider both the clients have a cached copy of a particular memory block from a previous read. When clients in a system maintain caches of a common memory resource, problems may arise with incoherent data, which is particularly the case with CPUs in a multiprocessing system. In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. Computer architecture term concerning shared resource data An illustration showing multiple caches of some memory, which acts as a shared resource Incoherent caches: The caches have different values of a single address location.
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